This invention relates to a method of manufacturing CMOS semiconductor devices, and more particularly to a method of forming a salicide (self-aligned silicide) structure used for lowering the resistances of the diffusion layers and gate electrodes of semiconductor elements.
A method of forming a conventional semiconductor element using the salicide technology is explained in detail with reference to FIGS. 18 to 23 by taking a case of CMOS integrated circuit as an example. As shown in FIG. 18, a p-type well 2 and an n-type well 3 are selectively formed on a semiconductor substrate 1 by use of the ion-implantation technique or the like respectively in regions in which n-channel and p-channel MOS transistors are to be formed. Then, an element isolation insulating film 4 for isolating the element regions from each other is formed by use of an element isolation method such as a LOCOS method.
Next, as shown in FIG. 19, a gate insulating film 5 is formed on the semiconductor substrate and a polysilicon film 6 used as a gate material is formed on the gate insulating film. Then, an insulating film 7 such as a silicon dioxide film or silicon nitride film used as a cap material is formed on the polysilicon film. After this, a resist is coated and patterned.
A patterned resist is used as a mask to etch the cap material 7, the pattern of the patterned resist is transferred on the cap material 7 as shown in FIG. 20, and then the resist is removed.
Next, as shown in FIG. 21, the gate material 6 and gate insulating film 5 are selectively removed by an anisotropic etching process with the cap portions 7 used as a mask.
Then, as shown in FIG. 22, the cap portions 7 are removed. Shallow n-type and p-type diffusion layers 8, 9 of relatively low impurity concentration are respectively formed in the p-type well for the n-type transistor and the n-type well for the p-type transistor so as to form an LDD structure, if required. Then, an SiN film is formed over the entire surface and selectively etched by the anisotropic etching process to form side walls 10 of SiN film, and then ion-implantation is effected so that diffusion layers 11, 12 and formed in the p-type well 2 and n-type well 3, respectively, and at the same time, the gate portions 6 are ion-doped.
Next, as shown in FIG. 23, a refractory metal film is formed by a sputtering method or the like, and by effecting an adequate heat treatment, contact regions between the silicon surface portions and the refractory metal film, that is, the upper surface portions of the gate portions 6 and the surface portions of the semiconductor substrate are converted into silicide as indicated by a reference numeral 13. Then, a portion of the refractory metal film which is not used for silicide reaction, that is, an unreacted portion thereof is removed so as to form a semiconductor element utilizing the salicide technique.
Next, the reason why the pattern of the resist is transferred onto the cap material as described above is explained. As shown in FIG. 24, an insulating film 31 used as a gate insulating film is formed on a semiconductor substrate 30 and a polysilicon film 32 used as a gate electrode is formed on the insulating film.
After this, in order to form the gate electrode, the polysilicon film 32 and insulating film 31 are selectively etched by the anisotropic etching process with a patterned resist 33 used as a mask.
As the size of recent semiconductor elements is reduced, the distance W between the adjacent gate electrodes tends to be made shorter. When a region 20 of polysilicon film 32 and insulating film 31, between the adjacent gate electrodes is etched, an etchant gas cannot be sufficiently supplied to the region 20 if the distance W is short, and as a result, the etching process for the region will not smoothly proceed and it becomes necessary to prolong the etching time. In this case, the resist film thickness L must be made large accordingly. If the resist film thickness L is made large, the patterning precision of the resist pattern is lowered in the lithography process. Further, if the resist film thickness L is made large, it becomes more difficult to sufficiently supply the etchant gas to the region 20 in the etching process.
In order to solve the above problem, a cap material 35 formed of a thin insulating film is formed between the resist 33 and the polysilicon film 32 as shown in FIG. 25, and then the resist pattern is transferred to the cap material 35 by use of the anisotropic etching process (not shown). After this, the resist film 33 is removed and gate electrodes (not shown) are formed by the anisotropic etching process by using the cap portions 35 as a mask.
That is, by taking the above procedure, the cap portions 35 which are sufficiently thinner (M&lt;N) than the resist 33 are used as a mask instead of the resist 33 so that the etchant gas can be sufficiently supplied to the region 20 between the gate electrodes without increasing the distance W between the gate electrodes. Therefore, in order to form a small-sized semiconductor element, the cap portions 35 are indispensable.
However, when both of the cap portions and the salicide technique are used and if the cap portions are formed on the polysilicon film which is used as the gate electrode, then the polysilicon film is not converted into silicide and the gate resistance becomes high, and therefore, the cap portions must be removed before formation of salicide (refer to FIG. 21 and FIG. 22).
Use of a self-aligned contact (SAC) is an effective technique for high integration density, but since the technique cannot be used if an insulating cap portion is not formed on the gate, it becomes impossible to simultaneously use the above technique and the salicide technique which is based on the condition that the cap portion is removed.
As described above, use of the cap portion is indispensable in order to form a small-sized semi-conductor element. However, in a case where the salicide technique is used at this time, the polysilicon film is not converted into silicide and the gate resistance becomes high if the cap portion is formed on the polysilicon film which is used as the gate electrode, and therefore, the cap portion must be removed before formation of salicide.
Further, since the self-aligned contact (SAC) cannot be used if an insulative cap portion is not formed on the gate electrode, it becomes impossible to simultaneously use the self-aligned contact and the salicide technique which is based on the condition that the cap portion is removed.